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Patterning Scheme Analysis of Extra Mini SlitĪt the 32P TCAT process node, 1 of 4 memory cells can be exclusively addressed between any two slits using a combination of bitlines and wordlines.

Enhancing device density without sacrificing the allowed process window is a key issue in 3D NAND process development. These narrower process windows are needed so that the downstream stair contact will precisely land on the staircase center without shorting the word line at the stair sidewall. Also, shrinking the stair CD and pitch will require a more uniform stair angle along with a much smaller CD variation in the stair etch process. With a smaller channel hole pitch and CD, the allowed process window for other processes (such as the channel hole to channel hole bridge during the etch process, or the channel hole to substrate open in both the etch and deposition processes) will become narrower. For example, if the slit pitch is reduced, the channel hole pitch must also be decreased at the same time. Unfortunately, these changes can introduce many challenges in lithography and downstream etch and gap filling processes. Traditionally, memory cell and staircase area could be reduced by decreasing the CD and pitch of the slit and stair structures. In 3D NAND, slit pitch in the bitline direction, and stair pitch in the cross bitline direction, are two of the most important factors in determining memory cell and staircase area. The Effect of Patterning Schemes on the Process Window